Design and Analysis of an Efficient Wallace Tree Multiplier using Current Comparison Domino

In this paper, a new domino circuit is proposed with low leakage current and high noise immunity which decreases the parasitic capacitance on the dynamic node. This yields a smaller keeper transistors for wide fan-in gates to implement fast and robust circuits. The technique utilized is based on comparison of mirrored current of the pull-up network with its worst case leakage current. Thus, the power consumption and delay can be reduced. A 6*6 Wallace tree multiplier is designed based on CCD (Current Comparison Domino) which uses low leakage high speed full adders. These full adders uses current comparison based domino logic to achieve low leakage and high speed. The proposed design is simulated using LT SPICE schematic editor tool.